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An end-to-end compilation stack for mapping ML kernels onto spatial hardware architectures.
GitHub →An MLIR-backed compiler pipeline for exploring spatial hardware mappings and generating constraint models for dataflow accelerators.
GitHub →Open-source tool for CGRA accelerators — compilation, simulation, and design space exploration.
GitHub →Portable framework for DFG mapping on spatial accelerators using graph neural networks.
GitHub →CGRA with flexible execution paradigm supporting spatio-temporal vector dataflow.
GitHub →Data-Aware Offloading and Predictive Pre-Calculation for efficient MoE inference.
GitHub →Simulator for the HyCUBE CGRA architecture with reconfigurable single-cycle multi-hop interconnect.
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